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Freescale Semiconductor /MK61F15WS /SIM /SCGC1

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Interpret as SCGC1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0 (0)OSC1 0RESERVED 0 (0)UART4 0 (0)UART5 0RESERVED

UART4=0, UART5=0, OSC1=0

Description

System Clock Gating Control Register 1

Fields

RESERVED

no description available
OSC1

OSC1 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
RESERVED

no description available
UART4

UART4 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
UART5

UART5 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
RESERVED

no description available

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data