Regviz

Freescale Semiconductor /MK61F15WS /SIM /SCGC1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCGC1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MK61F15WS/SIM/SCGC1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0 (0)OSC1 0RESERVED 0 (0)UART4 0 (0)UART5 0RESERVED

UART5=0, OSC1=0, UART4=0

Description

System Clock Gating Control Register 1

Fields

RESERVED

no description available
OSC1

OSC1 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
RESERVED

no description available
UART4

UART4 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
UART5

UART5 clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.
RESERVED

no description available

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data